library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--分频，不一样的频率对应不一样的音，
entity freq_divide is
port(
      clk1:in STD_LOGIC;
		tone1:in INTEGER range 0 to 47781;
		spks:out STD_LOGIC);
end entity freq_divide;

architecture art of freq_divide is
  signal preclk: STD_LOGIC;
  signal fullspks: STD_LOGIC;
  signal full: STD_LOGIC;
begin

--process(clk1)    --分频，2分频，preclk是16MHz的，相当于半秒为一拍
--  variable count: INTEGER range 0 to 8:=0;
--begin
--  if(clk1'event and clk1='1') then    
--    count := count+1;      --变量赋值
--	 if count=2 then
--	   preclk<='1';         --信号赋值
--    elsif count=4 then
--	   preclk <= '0';
--		count := 0;
--	 else
--	 end if;
--  end if;
--end process;

process(clk1,tone1)    --preclk转化成音符的频率，要是还没有到达
  variable count11: INTEGER range 0 to 47781;
begin
  if(clk1'event and clk1='1') then     --也是个分频，分出音符的频率
	 if count11 < tone1 then      --计数器count11计数值<tone1,fullspks高电平
	   count11:=count11+1;
		fullspks<='1';             --fullspks是音符的频率
	 else
		count11:=0;
		fullspks<='0';
	 end if;
  end if;
end process;

process(fullspks)    --分频，2分频，preclk是16MHz的，相当于半秒为一拍
 begin
  if(fullspks'event and fullspks='0') then    
    full<=not full;
  end if;
end process;

spks<=full;
--
--process(fullspks)
--  variable count2: INTEGER range 0 to 1:=0;
--begin
--  if(fullspks'event and fullspks='1') then     --如果是fullspks是高电平就让蜂鸣器响
--    if count2=1 then 
--	   count2:=0;
--	 else
--	   count2:=1;   
--	 end if;
--	 if count2=1 then   
--	    spks<='1';
--	 else
--	    spks<='0';
--	 end if;
--  end if;
--end process;
end art;
		 
		 
		 
		 
		 
		 
		 
		 
		 
		 
		 
		 
		 
		 
  
		  























